As the components of semiconductor devices shrink to smaller and smaller sizes, now on the order of nanometers, the ability to improve metrology performance, productivity, and device correlation becomes ever so important. To determine the alignment of features formed in one layer with respect to features formed in a previous or subsequent layer, metrology targets are often formed in one or more of the layers. The metrology targets facilitate measurement of the dimensions of features and alignment, e.g., overlay, between the features using a metrology tool such as a critical dimension (CD) scanning electron microscope (SEM) or scatterometer. In the past, metrology target optimization was performed experimentally by trial and error, and by “rules of thumb” based on prior experience. Currently, metrology engineers work with GDS metrology target libraries or collaborate with layout engineers to modify generic target designs based on known rules of thumb in order to do a best effort to make metrology structures compatible lithographic design rules, process constraints and metrology performance considerations.
Unfortunately, in a trial and error approach each trial represents a new reticle and a set of experiments with the new reticle to test the performance of the target. This is often a time consuming approach. It can sometimes take up two or three mask design iterations until the design is satisfactory. Consequently, trial and error based design tends to be slow and costly. In addition “rules of thumb” are often considered intellectual property, so widespread dissemination of the rules themselves may not possible. Furthermore, the conventional approach requires technical inputs from a number of different domain experts who are not always available to support the metrology engineer. Furthermore, such an approach can result in target designs which are suboptimal in the area of lithography compatibility, process compatibility or metrology compatibility. Consequently, lack of new target adoption and/or suboptimal targets were often the result of this approach.
It is within this context that embodiments of the present invention arise.